Intel Will Be Equipped with Upcoming Cannonlake 10nm Processor With AVX-512 Support

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So much the curiosity of many people about the existence of next-generation Intel 10-nanometer processor, seems to have responded by Intel by way of disclosing the discussion through one of its PDF document posting on its official website recently. According to “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, either Cannon Lake or the upcoming Ice Lake, reportedly will both carry the support of Advanced Vector Extensions (AVX) 512 instruction (along with a number of other instructions).
Intel 10nm with AVX-512 Support
AVX-512 itself first appeared on Intel Xeon Phi processor and coprocessor, and then continued on Intel Xeon Scalable processor. The instructions are designed to accelerate centrally managed workstation and server performance, such as scientific simulation, financial analysis, 3D modeling, image and audio / video processing, cryptography, data compression, artificial intelligence, and in-depth learning.

But with more and more people focusing on AI and deep-learning technology, it is not wrong if Intel continues to be consistent to plan to present a processor model that supports these indispensable instructions. Thanks to the presence of processors such as Cannon Lake and Ice Lake that support various AVX-512 instructions, including AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL, it makes practically the developers will have the opportunity to do things that are not possible with Kaby processor Lake and Coffee Lake.
The Intel AVX-512 instruction is very important as it unlocks higher performance capabilities for the most demanding computing tasks though. Intel Instructions AVX-512 offers the highest level of compiler support by including an unprecedented level of richness in instructional design capabilities.
The Intel AVX-512 features 32 vector registers, each containing 512-bit and eight special mask registers. The Intel AVX-512 is a flexible set of instructions that includes support for broadcast, embeded masking allowing predication, floating point embeded floating point control, embedded floating point error tapping, instruction deployment, high speed math instruction, and compact representation of large displacement values.
One thing that remains unclear so far, whether the instruction will be limited to higher end SKUs, such as Core i7 chips or Extreme Edition variants. On the hardware side itself, with the addition of AVX-512 support means the die size will be much larger and the cost is also higher. As for the software support, it must be constantly updated (or built) to support the latest AVX-512 instruction.

Meanwhile, Intel recently had to showcase the existence of Cannon Lake processor for the first time. The chip maker reportedly will soon market its first Cannon Lake processor product at the end of the year, followed by mass production in the first half of 2018.

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